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HA-5170
TM
Data Sheet
July 2000
File Number
2912.4
8MHz, Precision, JFET Input Operational Amplifier
The Intersil HA-5170 is a precision, JFET input, operational amplifier which features low noise, low offset voltage and low offset voltage drift. Constructed using FET/Bipolar technology, the Intersil Dielectric Isolation (DI) process, and laser trimming this amplifier offers low input bias and offset currents. This operational amplifier design also completely eliminates the troublesome errors due to warm-up drift. Complementing these excellent input characteristics are dynamic performance characteristics never before available from precision operational amplifiers. An 8V/s slew rate and 8MHz bandwidth allow the designer to extend precision instrumentation applications in both speed and bandwidth. These characteristics make the HA-5170 well suited for precision integrator amplifier designs. The superior input characteristics also make the HA-5170 ideally suited for transducer signal amplifiers, precision voltage followers and precision data acquisition systems. For application assistance, please refer to Application Note AN540 addressing specifically this device.
Features
* Low Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 100V * Low Offset Voltage Drift . . . . . . . . . . . . . . . . . . . . . 2V/oC * Low Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10nV/ Hz * High Open Loop Gain. . . . . . . . . . . . . . . . . . . . . . 600kV/V * Wide Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8MHz * Unity Gain Stable
Applications
* High Gain Instrumentation Amplifiers * Precision Data Acquisition * Precision Integrators * Precision Threshold Detectors * For Further Design Ideas, Refer to Application Note 540
Ordering Information
PART NUMBER HA7-5170-5 TEMP. RANGE (oC) 0 to 75 PACKAGE 8 Ld CERDIP PKG. NO. F8.3A
Pinout
HA-5170 (CERDIP) TOP VIEW
BAL -IN +IN V1 2 3 4 8 NC
+
7 V+ 6 OUT 5 BAL
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000
HA-5170
Absolute Maximum Ratings
Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . 44V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V Output Short Circuit Duration. . . . . . . . . . . . . . . . . . . . . . . Indefinite Operating Conditions Temperature Range HA-5170-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 115 28 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
VSUPPLY = 15V, Unless Otherwise Specified HA-5170-5 TEST CONDITIONS TEMP. (oC)
PARAMETER INPUT CHARACTERISTICS Offset Voltage
MIN
TYP
MAX
UNITS
25 Full
10 1 x 1010 -
0.1 2 20 0.1 3 3 0.3 +15.1 -12 80 6 x 1010 12 0.5 20 12 10 0.05 0.01 0.01
0.3 0.5 5 100 2 60 0.1 1 100 5 150 50 25 0.1
mV mV V/oC pA nA pA/oC pA nA pA/oC V V pF pF VP-P nV/ Hz nV/ Hz nV/ Hz pA/ Hz pA/ Hz pA/ Hz
Average Offset Voltage Drift (Note 3) Bias Current
Full 25 Full
Bias Current Average Drift Offset Current
Full 25 Full
Offset Current Average Drift (Note 3) Common Mode Range
Full Full Full
Differential Input Capacitance Differential Input Resistance (Note 3) Input Capacitance (Single Ended) Input Noise Voltage (Note 3) Input Noise Voltage Density (Note 3) 0.1Hz to10Hz f = 10Hz f = 100Hz f = 1000Hz Input Noise Current Density (Note 3) f = 10Hz f = 100Hz f = 1000Hz
25 25 25 25 25 25 25 25 25 25
2
HA-5170
Electrical Specifications
VSUPPLY = 15V, Unless Otherwise Specified (Continued) HA-5170-5 PARAMETER TRANSFER CHARACTERISTICS Large Signal Voltage Gain VOUT = 10V, RL = 2k VCM = 10V 25 Full Full 25 AVCL = +1 25 300 250 90 1 4 600 100 8 kV/V kV/V dB V/V MHz TEST CONDITIONS TEMP. (oC) MIN TYP MAX UNITS
Common Mode Rejection Ratio Minimum Stable Gain Closed Loop Bandwidth OUTPUT CHARACTERISTICS Output Voltage Swing Full Power Bandwidth (Note 4) Output Current (Note 5) Output Resistance (Note 3) TRANSIENT RESPONSE Rise Time Slew Rate Settling Time (Notes 3, 6) POWER SUPPLY CHARACTERISTICS Supply Current Power Supply Rejection Ratio (Note 7) NOTES: 2. See "Test Circuits and Waveforms" section.
RL = 2k RL = 2k VOUT = 10V Open Loop, 100Hz
25 25 25 25
10 80 10 -
12 120 15 45
100
V kHz mA
Note 2 Note 2
25 25 25
5 -
45 8 1
100 5
ns V/s s
Full Full
90
1.9 105
2.5 -
mA dB
3. Parameter is not 100% tested. 90% of all units meet or exceed these specifications. Slew Rate 4. Full power bandwidth guaranteed based on slew rate measurement using: FPBW = ---------------------------- . 2V PEAK 5. I turns on at 23mA.
SC
6. Settling time is measured to 0.1% of final value for a 10V output step and AV = -1. 7. V+ = +15V, V- = -10V to -20V and V- = -15V, V+ = +10V to +20V.
Test Circuits and Waveforms
V+ 7 3 + 2 6 OUT 5 1 4 100k VIN +
2k 50pF
OUT
-
Tested Offset Adjustment Range is |VOS + 1mV| minimum referred to output. Typical range is 5mV with RT = 1k and 15mV with RT = 100k. FIGURE 1. VOS ADJUSTMENT FIGURE 2. LARGE AND SMALL SIGNAL RESPONSE CIRCUIT
3
HA-5170 Test Circuits and Waveforms
(Continued)
Vertical Scale: 5V/Div. Horizontal Scale: 1s/Div. LARGE SIGNAL RESPONSE
Vertical Scale: 10mV/Div. Horizontal Scale: 100ns/Div. SMALL SIGNAL RESPONSE
+15V
100
3 +
7 6 3.5k OUT
100
2
4 -15V 4.7F
2.5M
10Hz FILTER
AV = 25,000
Vertical Scale: 200nV/Div. (Noise Referred to Input) 5mV/Div. at Output, AVCL = 25,000 Horizontal Scale: 1s/Div. HA-5170 LOW FREQUENCY NOISE (0.1HZ TO 10HZ)
FIGURE 3.
LOW FREQUENCY NOISE TEST CIRCUIT
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Schematic Diagram
V+ R13 Q23 R12 Q19 Q14 Q21 R14 Q31 Q32 J3 Q35 D2 Q22 Q30 Q42 D1 NC J5 -INPUT D5 +INPUT J1 C1 J2 R18 Q37 D4 C3 Q11 Q26 Q29 Q28 R17 R16 Q10 Q13 R7 OUT Q12 R19 Q43 Q47 J4 Q45 Q24 Q7 R8 D3 Q15 Q16 Q3 Q4 Q44 R6 Q36 Q33 R20
Q48
R9
Q46
R10
R11
R5
5
Q8
HA-5170
Q27
Q25 Q9 Q34
Q51
Q21
R23
Q6 R24
Q40 Q39 Q41 R3 Q49 Q20 R22 R1 R2 BAL C2 R4 BAL Q17 Q38 Q1 Q5 R15 R21 Q50
Q18
Q52
V-
HA-5170 Typical Performace Curves
1000 INPUT NOISE CURRENT (pA/Hz) INPUT NOISE VOLTAGE (nV/Hz) 0.6 0.5 0.4 OFFSET VOLTAGE (mV) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 1 1 10 100 1K FREQUENCY (Hz) 10K 0.001 100K -0.6 -55 -25 0 25 50 75 TEMPERATURE (oC) 100 125
100 INPUT NOISE CURRENT
0.1
10
INPUT NOISE VOLTAGE
0.01
FIGURE 4. INPUT NOISE vs FREQUENCY
FIGURE 5. OFFSET VOLTAGE DRIFT vs TEMPERATURE OF REPRESENTATIVE UNITS
10 10 OUTPUT VOLTAGE STEP (V) 10mV 5 1mV IBIAS (nA) 1 SETTLING TIME (s) 1.5 1
0 1mV -5 10mV -10
0.1
0.01
0
0.5
0.001 -50
-25
0
25 50 75 TEMPERATURE (oC)
100
125
FIGURE 6. SETTLING TIME FOR VARIOUS OUTPUT STEP VOLTAGES
FIGURE 7. BIAS CURRENT vs TEMPERATURE
NORMALIZED PARAMETERS REFERRED TO PARAMETERS AT 25oC
3
1.2
SUPPLY CURRENT (mA)
1.1 BANDWIDTH 1.0 SLEW RATE 0.9
2
125oC 25oC -55oC
1
5
10 15 SUPPLY VOLTAGE (V)
20
0.8 -55
-25
0
25
50
75
100
125
TEMPERATURE (oC)
FIGURE 8. POWER SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 9. NORMALIZED AC PARAMETERS vs TEMPERATURE
6
HA-5170 Typical Performace Curves
(Continued)
120 100 PSRR (dB) 80 60 40 20 PSRRPSRR+ CMRR (dB)
120 100 80 60 40 20
10
100
1K 10K FREQUENCY (Hz)
100K
1M
10
100
1K 10K FREQUENCY (Hz)
100K
1M
FIGURE 10. POWER SUPPLY REJECTION RATIO vs FREQUENCY
FIGURE 11. COMMON MODE REJECTION RATIO vs FREQUENCY
RL = 2k 60 PHASE MARGIN (DEGREES) 50 40 30 20 PHASE MARGIN 10 0 10 1 0 100 1000 10000 LOAD CAPACITANCE (pF) BANDWIDTH 6 UNITY GAIN BANDWIDTH (MHz) 5 4 3 2 OUTPUT VOLTAGE SWING (VP-P)
28 15V SUPPLIES 24 20 10V SUPPLIES 16 8 4 0 1K 5V SUPPLIES
RL = 2k CL = 50pF
10K 100K FREQUENCY (Hz)
1M
FIGURE 12. SMALL SIGNAL BANDWIDTH AND PHASE MARGIN vs LOAD CAPACITANCE
FIGURE 13. OUTPUT VOLTAGE SWING vs FREQUENCY AND SUPPLY VOLTAGE
TA = 25oC OUTPUT VOLTAGE SWING (VP-P)
35 30 25 20 15 10 5 0 100 VS = 5V VS = 10V
VS = 15V
NORMALIZED AC PARAMETERS REFERRED TO VALUE AT 15V
1.0 BANDWIDTH 0.8 0.6 0.4 SLEW RATE 0.2 0 2 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V)
1K 10K LOAD RESISTANCE ()
100K
FIGURE 14. NORMALIZED AC PARAMETERS vs SUPPLY VOLTAGE
FIGURE 15. MAXIMUM OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
7
HA-5170 Typical Performace Curves
110 100 OPEN LOOP VOLTAGE GAIN (dB) 90 80 70 60 50 40 30 20 10 0 -10 10 100 1K 10K 100K 1M FREQUENCY (Hz) 10M 180 100M 0 10 100 1K 10K 100K FREQUENCY (Hz) 1M 10M 100M PHASE 135 90 GAIN PHASE (DEGREES) 45 CLOSED LOOP GAIN (dB) 0 80 RL = 2k CL = 50pF 100
(Continued)
60
40
20
FIGURE 16. OPEN LOOP FREQUENCY RESPONSE
FIGURE 17. CLOSED LOOP FREQUENCY RESPONSE FOR VARIOUS CLOSED LOOP GAINS
8
HA-5170 Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A - B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.405 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 10.29 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
eA
c1 D E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 8 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 8 5.08 1.52 105o 0.38 0.76 0.25 0.038
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH
aaa bbb ccc M N
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369
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